1. Field of the Invention
The present invention relates to a chip inductor including alternately laminated conductor patterns and insulating layers constituting a coil, as well as a method for manufacturing the same.
2. Description of the Related Art
A chip inductor in the shape of a small, low-profile chip in outline is one type of extremely high performance, versatile electronic component compatible with miniaturization and slimming of electronic equipment. The chip inductor is incorporated into various electronic circuits, and is used as a noise filter, for example.
A first example of known technologies related to this type of inductor is a technology disclosed in Japanese Unexamined Patent Application Publication No. 9-17634, for example. This inductor is a laminated inductor constructed by alternately laminating coil conductors and low dielectric constant insulating films on an insulating substrate, and connecting the coil conductors located on and under the individual low dielectric constant insulating film to each other through a window portion provided in the low dielectric constant insulating film (so-called interlayer connection), so as to form one series of a coil connected in series in the entire chip inductor. In this laminated inductor, laminates of the coil conductors and the low dielectric constant insulating films are further layered to increase the inductance of the above-described one series of coil as a whole. That is, the total number of turns of the entire coil is increased and, thereby, a desired high inductance value is attained while the line width and the thickness of each coil conductor are ensured to achieve a reduction in direct-current resistance. As a result, realization of excellent Q characteristic is possible.
A second known technology is a technology disclosed in Japanese Unexamined Patent Application Publication No. 2002-246231, for example. In this technology, coil conductors having a large number of turns are disposed on an upper layer side and a lower layer side of the laminate in the above-described laminated inductor, and coil conductors having a small number of turns are disposed as intermediate layers sandwiched between the upper layer and the lower layer, so that the distribution of the direct-current resistance value is non-uniform throughout the coil. That is, the middle portion (intermediate layer portion) of the laminate has low direct-current resistance, and the portions nearer to the outside, such as the upper layer and the lower layer, have high direct-current resistance. In this manner, it is attempted to reduce the pressure bonding strain during production of the laminate, as well as to improve the heat dissipation characteristics of the laminated inductor.
However, in the above-described first known technology, the following problems may occur.
That is, when the laminates of the coil conductors and the low dielectric constant insulating layers are further layered to increase the inductance of the entire coil, although the line width may not be reduced, the thickness (height) of the external dimension of the entire laminate is increased by the thickness of the further layered portion. Therefore, advantages of the chip inductor, i.e. small size and low profile, may be impaired.
In the second technology, since the coil conductors having the large number of turns are disposed on the upper layer side and the lower layer side of the laminate, excellent heat dissipation characteristics can be attained while the inductance is increased. However, with respect to the layers having the small number of turns, the line width of the coil conductor must be increased in order to reduce the direct-current resistance value. Consequently, the inner diameter of the coil is decreased correspondingly, the inductance is decreased, and the Q characteristic may be reduced. Furthermore, with respect to the layers having the large number of turns, setting of the line width is restricted. Therefore, when this layer is fired during the manufacturing of a chip inductor, the line width of this layer is decreased by shrinkage and, as a result, there is also a problem in that the direct-current resistance value is increased.